Image sensor, pixel array, and operation method of the image sensor

ABSTRACT

An image sensor includes a pixel array including a pixel array comprising a first pixel and a second pixel which are electrically connected to a first column line, a row driver configured to receive a clamp voltage and a selection voltage, select the first pixel based on the clamp voltage and select the second pixel based on the selection voltage. A voltage of the first column line is determined based on a higher voltage among a first output voltage of the first pixel and a second output voltage of the second pixel during a read operation of the second pixel.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part application of U.S. Ser. No. 16/445,754, filed on Jun. 19, 2019, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0073771, filed on Jun. 27, 2018 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

TECHNICAL FIELD

Exemplary embodiments of the inventive concept relate to an image sensor and a pixel array, and more particularly, to an image sensor and a pixel array which generate a pixel signal based on a plurality of pixels.

DISCUSSION OF RELATED ART

An image sensor is an apparatus that captures a two-dimensional or a three-dimensional image of an object. The image sensor generates an image of an object by using a photoelectric converting device that responds to an intensity of light reflected from the object. Recently, with the development of complementary metal-oxide-semiconductors (CMOS), CMOS image sensors have been widely used.

SUMMARY

According to an exemplary embodiment of the inventive concept, an image sensor includes a pixel array including a pixel array comprising a first pixel and a second pixel which are electrically connected to a first column line, a row driver configured to receive a clamp voltage and a selection voltage, select the first pixel based on the clamp voltage and select the second pixel based on the selection voltage. A voltage of the first column line is determined based on a higher voltage among a first output voltage of the first pixel and a second output voltage of the second pixel during a read operation of the second pixel.

According to an exemplary embodiment of the inventive concept, a pixel array includes a first row pixel comprising a first selection transistor receiving a clamp voltage and the first row pixel configured to generate a first output voltage in response to receiving the clamp voltage; and a second row pixel comprising a second selection transistor receiving a selection voltage configured to generate a second output voltage based on an output of a photodiode and the selection voltage. A voltage applied to a column line connected to the first row pixel and the second row pixel is a voltage based on at least one of the first pixel signal and the second pixel signal.

According to an exemplary embodiment of the inventive concept, in an operation method of an image sensor including a first pixel and a second pixel, the operation method comprising, performing a reset operation to reset the first pixel and the second pixel, during a reset operation, turning off a first selection transistor of the first pixel and turning on a second selection transistor of the second pixel based on a selection voltage, performing a read operation based on an output of a photodiode of the second pixel, during the read operation, turning on the first selection transistor which is turned off based on clamp voltage, and maintaining the second selection transistor in a turn on state based on the selection voltage and outputting a higher level voltage as a pixel signal among a first output voltage of the first pixel and a second output voltage of the second pixel to a column line to which the first pixel and the second pixel are electrically connected.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.

FIG. 1 is a block diagram of an image sensor according to an exemplary embodiment of the inventive concept.

FIG. 2 is a block diagram of the image sensor of FIG. 1 according to an exemplary embodiment of the inventive concept.

FIGS. 3A and 3B illustrate a clamp controller according to exemplary embodiments of the inventive concept.

FIG. 4 illustrates a pixel array according to an exemplary embodiment of the inventive concept.

FIG. 5 illustrates an equivalent circuit of a winner-take-all circuit according to an exemplary embodiment of the inventive concept.

FIG. 6 is a timing diagram of an image sensor operation when a pixel signal is not clamped according to an exemplary embodiment of the inventive concept.

FIG. 7 is a timing diagram of an image sensor operation when a pixel signal is clamped according to an exemplary embodiment of the inventive concept.

FIG. 8 illustrates the image sensor of FIG. 1 in a reset state according to an exemplary embodiment of the inventive concept.

FIG. 9 illustrates the image sensor of FIG. 1 after a reset is completed according to an exemplary embodiment of the inventive concept.

FIG. 10 is a flowchart of an operation of an image sensor according to an exemplary embodiment of the inventive concept.

FIG. 11 is a flowchart of a particular operation method of an image sensor according to an exemplary embodiment of the inventive concept.

FIG. 12 is a block diagram of an image processing system according to an exemplary embodiment of the inventive concept.

FIG. 13 is a circuit diagram of a clamp controller according to an example embodiment of the inventive concept;

FIG. 14 is a circuit diagram of an operation of a pixel array according to an example embodiment of the inventive concept;

FIG. 15 is a graph explaining a relationship between a clamp voltage and an analog gain according to an example embodiment of the inventive concept;

FIG. 16 is a flowchart of an operation of an image sensor according to an example embodiment of the inventive concept;

FIG. 17 is a timing diagram of an operation of an image sensor when a pixel signal is not clamped according to an embodiment of the inventive concept; and

FIG. 18 is a timing diagram of an operation of an image sensor when a pixel signal is clamped according to an embodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept provide an image sensor and a pixel array configured to detect a pixel signal output from a pixel to which a photocharge is applied, by using another pixel.

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings Like reference numerals may refer to like elements throughout this application.

FIG. 1 is a block diagram of an image sensor according to an exemplary embodiment of the inventive concept.

An image sensor 100 may include a pixel array 110, a row driver 120, an analog to digital converter 130 (hereinafter referred to as an ADC 130), a timing generator 170, and a buffer 180.

The image sensor 100 may be mounted on an electronic device which has an image or light detecting function. For example, the image sensor 100 may be mounted on an electronic device such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation apparatus, or the like. In addition, the image sensor 100 may be mounted on an electronic device configured as a component in a vehicle, furniture, a manufacturing facility, a door, various measuring instruments, or the like.

The pixel array 110 may be accessed via a plurality of row lines RL and a plurality of column lines CL, and include a plurality of pixels arranged in a matrix form. Each of the plurality of pixels may include a light detecting device. The light detecting device may generate a photocharge in response to light incident from outside, and the plurality of pixels may convert the photocharge into a voltage or a current and output the same as a pixel signal PXS.

The row driver 120 may drive the pixel array 110 in row units. The row driver 120 may select at least one row line RL of the pixel array 110 according to a control signal CTR received from the timing generator 170. A pixel connected to the selected row line RL outputs the pixel signal PXS. The pixel signal PXS may include a reset signal and an image signal. The row driver 120 may control a read operation of a pixel. Hereinafter, the read operation may refer to an operation of resetting a pixel and outputting the pixel signal PXS of a size corresponding to a light intensity from the pixel.

The row driver 120 may include a clamp controller 121. The clamp controller 121 may transmit a clamp signal CLP for generating the pixel signal PXS in the pixel array 110. In addition, the clamp controller 121 may be electrically connected to at least one pixel among the plurality of pixels of the pixel array 110. In this case, a capacitor may be included between the clamp controller 121 and the at least one pixel. In addition, the clamp controller 121 may be electrically connected to a floating diffusion node FD of at least one of the plurality of pixels.

The clamp controller 121 may transmit either a first voltage or a second voltage as the clamp signal CLP according to the control signal CTR. In this case, the first voltage may be greater than the second voltage.

The ADC 130 converts an analog pixel signal input from the pixel array 110 into a digital signal. For example, the ADC 130 may generate a result of comparing the pixel signal PXS to a ramp signal so as to effectively detect a difference between the reset signal and the image signal. The ADC 130 may count signals output as a compared result and convert the signals into digital signals.

The timing generator 170 may generally control the image sensor 100. For example, an operation or a timing of the row driver 120 and the ADC 130 may be controlled by respectively transmitting the control signal CTR and a clock signal CLK to the row driver 120 and the ADC 130. For example, the timing generator 170 may provide the control signal CTR to the row driver 120 and the clamp signal CLP may be controlled. The clamp signal CLP may have different voltage values according to the control signal CTR.

After the buffer 180 temporarily stores a digital pixel signal DPS output from the ADC 130, the buffer 180 may sense and amplify the same and output the same as image data IDTA.

According to an exemplary embodiment of the inventive concept, the row driver 120 may apply the first voltage and the second voltage to the plurality of pixels of the pixel array 110, where the second voltage is less than the first voltage. A first pixel, which receives the second voltage, may be connected to a same column line CL as a second pixel. Accordingly, the pixel signal PXS may be determined according to at least one of an output voltage of the first pixel and the second pixel. In other words, the row driver 120 may provide the clamp signal CLP to the first pixel such that a voltage output from the second pixel may not be lower than a voltage of the first pixel. Accordingly, band noise generated when a second pixel output voltage value is excessively lowered due to an application of bright light to the second pixel may be controlled.

FIG. 2 is a block diagram of the image sensor of FIG. 1 according to an exemplary embodiment of the inventive concept.

The pixel array 110 may respectively be accessed via the plurality of row lines RL and the plurality of column lines CL and include a plurality of pixels 111 arranged in a matrix form. For example, the plurality of row lines RL may include four row lines RL, where each row line RL, as described later with reference to FIG. 4, may transmit a control signal to a reset transistor, a transfer transistor, and a selection transistor, and transmit a clamp signal to the pixels 111.

Each of the plurality of pixels 111 may include a light detecting device For example, the light detecting device may include a photodiode, a phototransistor, a port gate, a pinned photodiode, or the like. Each of the plurality of pixels 111 may include at least one light detecting device; for example, each of the plurality of pixels 111 may include a plurality of light detecting devices. The plurality of light detecting devices may be stacked on one another in an incident direction of light.

Each of the plurality of pixels 111 may detect light in a particular spectrum region. For example, the plurality of pixels 111 may include a red pixel converting light in a red spectrum region into an electric signal, a green pixel converting light in a green spectrum region into an electric signal, and a blue pixel converting light in a blue spectrum region into an electric signal. A color filter configured to transmit light in a particular spectrum region may be arranged above each of the plurality of pixels 111.

The plurality of pixels 111 may detect light by using the light detecting device and convert the light into the pixel signal PXS, which is an electrical signal. For example, the plurality of pixels 111 may emit many electrons (photocharges) when bright light is applied. A voltage value output from the light detecting device may be lowered with respect to brighter light. Band noise may occur when an output voltage value output from the light detecting device is excessively low.

The row driver 120 may, for example, drive the pixel array 110 in row units and control a read operation of at least one pixel 111. The row driver 120 may decode a row control signal (e.g.

an address signal) generated in the timing generator 170 and select at least one of the row lines RL in the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 may generate a row selection signal. The pixel array 110 may output the pixel signal PXS from the row selected by using the row selection signal provided from the row driver 120. For example, the pixel signal PXS may have one of a voltage corresponding to a reset state, a voltage corresponding to the photocharge, or a clamp voltage.

The clamp controller 121 may transmit the clamp signal CLP to at least one of the plurality of pixels 111. For example, the clamp controller 121 may apply the clamp signal CLP to a floating diffusion node of the pixel 111. Meanwhile, the row driver 120 may generate the row selection signal to select two row lines RL. For example, a signal selecting the plurality of pixels 111 included in a first row and a signal selecting the plurality of pixels 111 included in a second row may be generated. The clamp controller 121 may transmit the clamp signal CLP by alternately applying the first voltage or the second voltage to one row line RL out of the two selected row lines RL. For example, the first voltage may be greater than the second voltage. The first voltage may be a power supply voltage VDD and the second voltage may be a voltage which is lower than the power supply voltage VDD.

According to an exemplary embodiment of the inventive concept, the clamp controller 121 may apply the first voltage to the first pixel, while the row driver 120 turns on the reset transistor included in the pixels 111. In this case, a floating diffusion node of the first pixel may be maintained as a voltage corresponding to the first voltage, After the row driver 120 turns on the reset transistor included in the pixel 111, the clamp controller 121 may apply the second voltage to the first pixel. In this case, the floating diffusion node of the pixel 111 may change the voltage from a voltage corresponding to the first voltage to a voltage corresponding to the second voltage. Since the first voltage is greater than the second voltage, in a case where the clamp controller 121 applies the second voltage, a voltage size of the floating diffusion node may drop.

Meanwhile, the clamp controller 121 may maintain a line connecting the clamp controller 121 to the second pixel in an opened state. The row driver 120 may apply the second voltage to the first pixel and turn on the transfer transistor of the second pixel after a fixed time. Accordingly, a current and/or a voltage according to the photocharge output from the light detecting device of the second pixel may be applied to the floating diffusion node of the second pixel. A source follower transistor of the first pixel and the second pixel may connect to the floating diffusion node and the selection transistor of each pixel. In this case, the floating diffusion node may be connected to a gate terminal of the drive transistor and only a high source follower transistor having a high voltage at the floating diffusion node may apply a voltage to the column line CL through the selection transistor. Additionally, at least one of the transistors may include an NMOS transistor.

The ADC 130 may convert an analog pixel signal input from the pixel array 110 into a digital signal. The ADC 130 may include a comparison block 140 and a counter block 150.

The comparison block 140 compares the pixel signal PXS output from a unit pixel accessed via any one of the column lines CL in the pixel array 110 with a ramp signal RAMP. The comparison block 140 includes a plurality of comparison circuits 141 corresponding to each column, and each of the plurality of comparison circuits 141 is connected to the pixel array 110 and a ramp signal generator 160 generating the ramp signal RAMP.

Each comparison circuit 141 may receive and compare the pixel signal PXS to the ramp signal RAMP generated from the ramp signal generator 160, and a comparison result signal may be output to an output terminal of the comparison circuit 141.

The comparison circuit 141 may generate a comparison result signal to which a correlated double sampling technique is applied and may be referred to as a correlated double sampling circuit. The pixel signals PXS output from the plurality of pixels 111 may have a deviation due to a characteristic difference in logic for outputting the pixel signal PXS and/or a pixel-unique characteristic (e.g. fixed pattern noise) for each pixel. To compensate for a deviation between such pixel signals, obtaining a reset component (or a reset signal) and an image component (or an image signal) with respect to each of the pixel signals and extracting a difference between the reset component and the image component as a valid signal component is called correlated double sampling. As such, the comparison circuit 141 may output a comparison result signal to which the correlated double sampling technique is applied.

The ramp signal generator 160 may generate the ramp signal RAMP. The ramp signal generator 160 may operate based on a ramp control signal provided by the timing generator 170. The ramp control signal may include a ramp enable signal, a mode signal, or the like. The ramp signal generator 160 may generate the ramp signal RAMP having a slope set based on the mode signal when the ramp enable signal is activated.

The counter block 150 may include a plurality of counters 151. Each of the plurality of counters 151 may be connected to a corresponding output terminal of the comparison circuits 141, and may be counted based on an output of each comparison circuit 141. A counter control signal may include a counter clock signal, a counter reset signal controlling a reset operation of the plurality of counters 151, and an inversion signal inverting an internal bit of each of the plurality of counters 151. The counter block 150 counts the comparison result signal and outputs the same as a digital signal according to the counter clock signal.

The counter 151 may include an up/down counter, a bit-wise inversion counter, or the like. At this time, a bit-wise inversion counter may perform an operation similar to an up/down counter. For example, the bit-wise inversion counter may perform a function of producing a 1's complement by inverting all bits inside the bit-wise inversion counter when a function of performing only an up-count and a particular signal arrives. The bit-wise inversion counter may convert a reset count to a 1's complement, in other words, a negative value, by inverting the reset count after performing the reset count.

The buffer 180 may include a column memory block 181 and a sense amplifier 182, where the column memory block 181 may include a plurality of memories 183. Each of the plurality of memories 183 may temporarily store a digital signal output from a corresponding one of the plurality of counters 151, and may output the same to the sense amplifier 182. The sense amplifier 182 may sense and amplify the digital signal output from the plurality of memories 183. The sense amplifier 182 may output amplified digital signals as the image data IDTA.

Accordingly, the pixel signal PXS may be maintained above a certain voltage (e.g. a clamp voltage) value and various pieces of noise generated in the pixel 111 may be prevented during the read operation of the second pixel by alternately applying the first voltage and the second voltage to the floating diffusion node of the first pixel. In addition, a precise clamping technique may be realized since the first pixel, positioned adjacent to the second pixel and providing a low parasitic resistance value, may be operated as a clamping circuit without the need to design an additional layer or a circuit to remove the pieces of noise. In other words, the first pixel may operate as a pixel of a clamp row for clamping the voltage of the pixel signal PXS of the second pixel during the read operation of the second pixel.

FIGS. 3A and 3B illustrate a clamp controller according to exemplary embodiments of the inventive concept.

Referring to FIG. 3A, a clamp controller 121 a may output either a first voltage V1 or a second voltage V2 as the clamp signal CLP. The clamp controller 121 a may include a first switch S1 and a second switch S2, and may maintain an opened or a short-circuit state according to the control signal CTR applied from outside of the clamp controller 121 a. For example, the clamp controller 121 a may receive the first voltage V1 and the second voltage V2 and control at least one of the first switch Si and the second switch S2 to be in the opened or the short-circuit state according to the control signal CTR received from the timing generator 170. The clamp controller 121 a may output either the first voltage V1 or the second voltage V2 as the clamp signal CLP.

The clamp controller 121 a may alternately output the first voltage V1 and the second voltage V2 at a prefixed time interval. For example, the first voltage V1 may be applied to the first pixel and then the second voltage V2 may be applied during the read operation of the second pixel, and a voltage difference of the clamp signals may be made to be a difference between the first voltage V1 and the second voltage V2.

According to an exemplary embodiment of the inventive concept, in a case where the timing generator 170 applies a reset signal, the clamp controller 121 a may be controlled to make the first switch Si short-circuit and the second switch S2 be opened. Thereafter, the timing generator 170 may apply a selection signal to the first pixel and the second pixel, and then, after a prefixed time, the clamp controller 121 a may be controlled to make the first switch S1 be opened and the second switch S2 short-circuit.

Referring to FIG. 3B, a clamp controller 121 b may include a multiplexer (MUX). The

MUX may receive the first voltage V1 through a first input terminal and receive the second voltage V2 through a second input terminal, and output one of the voltages input to the input terminal according to the control signal CTR applied to a selection terminal. The clamp controller 121 b shown in FIG. 3B may perform a same or similar operation as the clamp controller 121 a shown in FIG. 3A, and thus a detailed description thereof will be omitted.

FIG. 4 illustrates a pixel array according to an exemplary embodiment of the inventive concept.

The pixel array 110 may include a first pixel 111 a and a second pixel 111 b, which are connected to a same column line CL. The first pixel 111 a and the second pixel 111 b may be pixels included in different rows. For example, the first pixel 111 a and the second pixel 111 b may be positioned in adjacent rows and at least one pixel is arranged between the first pixel 111 a and the second pixel 111 b. Although only one of the pixels included in each row is shown for convenience of explanation, each row may include a plurality of pixels.

Referring to FIG. 4, the first pixel 111 a and the second pixel 111 b may respectively include a reset transistor RX, a transfer transistor TX, a drive transistor DX, a selection transistor SX, a floating diffusion capacitor Cf, and a photodiode PD. In this case, the photodiode PD may be implemented as a different type of the light sensing device. In addition, the first pixel 111 a and the second pixel 111 b may receive a floating diffusion node voltage VFD and the clamp signal CLP, and may further include a clamp capacitor Cp connected with a clamp line. For example, the clamp line may extend in a row direction and be connected to pixels of different columns in a same row.

The pixel array 110 may reset the plurality of pixels in response to a control signal received from the row driver 120. The row driver 120 may respectively apply selection signals deactivated in gate terminals of a first selection transistor SX1 and a second selection transistor SX2 as a first selection signal SEL1 and a second selection signal SEL2. Hereinafter, a deactivated signal may be referred to as a low-level voltage (e.g. a voltage VSS, etc.) for logic low, and may be referred to as a high-level voltage (e.g. a voltage VDD, etc.) for logic high. Accordingly, outputs of the first pixel 111 a and the second pixel 111 b may be blocked. The row driver 120 may respectively apply selection signals deactivated in gate terminals of a first reset transistor RX1 and a second reset transistor RX2 as a first reset signal RS1 and a second reset signal RS2. Accordingly, a first floating diffusion node voltage VFD1 and a second floating diffusion node voltage VFD2 may be reset to the power supply voltage VDD.

The pixel array 110 may perform a clamping function in response to a control signal received from the row driver 120. For example, the pixel array 110 may clamp the pixel signal PXS by controlling a voltage output from the first pixel 111 a during a read operation of the second pixel 111 b.

According to an exemplary embodiment of the inventive concept, the row driver 120 may respectively apply selection signals deactivated in gate terminals of the first selection transistor SX1 and the second selection transistor SX2 as the first selection signal SEL1 and the second selection signal SEL2, and the row driver 120 may respectively apply selection signals deactivated in gate terminals of the first reset transistor RX1 and the second reset transistor RX2 as the first reset signal RS1 and the second reset signal RS2. In other words, the pixel array 110 may complete a reset operation.

Thereafter, the row driver 120 may apply the first clamp signal CLP1 to a first clamp capacitor Cp1 through the clamp line of the first pixel 111 a and adjust a first floating diffusion node voltage VFD1. In addition, the first floating diffusion node voltage VFD1 may be adjusted according to capacitance values of the first clamp capacitor Cp1 and a first floating capacitor Cf1, which are connected to a first floating diffusion node. For example, in a case where the first floating diffusion node voltage VFD1 has the power supply voltage VDD in a reset state, the first floating diffusion node voltage VFD1 may be determined according to the following Equation 1.

$\begin{matrix} {{{VFD}\; 1} = {{VDD} - \left\{ {\left( {{V\; 1} - {V\; 2}} \right) \times \frac{{Cp}\; 1}{C_{total}}} \right\}}} & {{Equation}\mspace{14mu} 1} \end{matrix}$

In Equation 1, C_(total) may be, for example, Cp1+Cf1, and may be a sum of all capacitances connected to the first floating diffusion node.

According to an exemplary embodiment of the inventive concept, in a case where the first clamp signal CLP1 is applied, the first floating diffusion node voltage VFD1 may be lower than a second floating diffusion node voltage VFD2. For example, in a case where the first voltage V1 is greater than the second voltage V2, the first floating diffusion node voltage VFD1, after a reset is completed, changes to a voltage lower than the power supply voltage VDD, which is a reset voltage. Since a second clamp signal CLP2 is not applied to the second pixel 111 b, the second floating diffusion node voltage VFD2 may be maintained as the power supply voltage VDD in a reset state. Accordingly, the first floating diffusion node voltage VFD1 changes to a level lower than the power supply voltage VDD, the second floating diffusion node voltage VFD2 may be maintained at a level of the power supply voltage VDD.

In this case, the row driver 120 may transmit a deactivated signal to a first transfer transistor TX1 as a first transfer signal TG1 during the read operation of the second pixel 111 b. A pixel that generates substantial image data according to a photocharge generated in the photodiode is the second pixel 111 b. Therefore, to prevent an output signal of a first photodiode PD1 from being output as the pixel signal PXS, the first transfer transistor TX1 may be maintained in a turn-off state during the read operation of the second pixel 111 b.

According to an exemplary embodiment of the inventive concept, the pixel signal PXS, which is a voltage output to the column line CL connected to the first pixel 111 a and the second pixel 111 b, may be determined based on the first floating diffusion node voltage VFD1 and the second floating diffusion node voltage VFD2, which will be described further with reference to FIG. 5.

FIG. 5 illustrates an equivalent circuit of a winner-take-all circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5, two transistors shown may be the drive transistor DX included in the pixel according to exemplary embodiments of the inventive concept. For example, a first transistor TR1 and a second transistor TR2 may respectively be a first drive transistor DX1 included in the first pixel 111 a and a second drive transistor DX2 included in the second pixel 111 b. Hereinafter, for the convenience of explanation, it is assumed that the first transistor TR1 and the second transistor TR2 are implemented as NMOS transistors.

According to an exemplary embodiment of the inventive concept, in a case where a first gate voltage VG1 of the first drive transistor TR1 is greater than a second gate voltage VG2 of the second transistor TR2, a voltage applied to a common node CN is equal to the value obtained by subtracting a gate-source voltage Vgs from the first gate voltage VG1. In other words, VG1−Vgs=VCN may be obtained. In addition, in a case where the first gate voltage VG1 of the first drive transistor TR1 is greater than the second gate voltage VG2 of the second transistor TR2, a bias current Io may be a value based on a first current I1 and a value which does not relate to a second current 12. Therefore, only a transistor having a large gate voltage level may operate, and a transistor having a low gate voltage level may not operate. This may be called a winner-take-all circuit. For example, referring to FIG. 5 and FIG. 4, a principle in which the voltage is applied to the common node CN in FIG. 5 is similar to a principle in which the voltage is applied as the pixel signal PXS in FIG. 4. In this case, the first gate voltage VG1 and the second gate voltage VG2 may respectively correspond to the first floating diffusion node voltage VFD1 and the second floating diffusion node voltage VFD2 in FIG. 4. This is because the first selection transistor SX1 and the second selection transistor SX2 are in a turn-on state during the read operation of the second pixel 111 b in FIG. 4.

Referring to FIG. 4 again, the pixel signal PXS output from the first pixel 111 a and the second pixel 111 b to the column line CL may be determined based on a high voltage between the first floating diffusion node voltage VFD1 and the second floating diffusion node voltage VFD2.

As described, the first drive transistor DX1 and the second drive transistor DX2 may be source follower transistors in winner-take-all circuits. In this case, a voltage value based on the second floating diffusion node voltage VFD2 may be a clamp voltage VCLP. When the first floating diffusion node voltage VFD1 is greater than the clamp voltage VCLP, a voltage applied as the pixel signal PXS may be the first floating diffusion node voltage VFD1. Conversely, when the first floating diffusion node voltage VFD1 is lower than the clamp voltage CLP, the voltage applied as the pixel signal PXS may be the clamp voltage VCLP. For example, the first floating diffusion node voltage VFD1 may be a voltage obtained by subtracting a gate-source voltage of the first drive transistor DX1 from the first floating diffusion node voltage VFD1. The second floating diffusion node voltage VFD2 may also be a voltage obtained by subtracting a gate-source voltage of the second drive transistor DX2 from the second floating diffusion node voltage VFD2.

According to an exemplary embodiment of the inventive concept, the first pixel 111 a may receive the first clamp signal CLP1 and generate a first pixel signal, and the second pixel 111 b may generate a second pixel signal based on photocharge received from a second photodiode

PD2. The pixel signal PXS generated by the first pixel 111 a is based on the first clamp signal CLP1, and the pixel signal PXS generated by the second pixel 111 b is based on the second photodiode PD2. For example, the first pixel signal may be a value obtained by subtracting the gate-source voltage of the first drive transistor DX1 from the first floating diffusion node voltage VFD1, and the second pixel signal may be a value obtained by subtracting the gate-source voltage of the second drive transistor DX2 from the second floating diffusion node voltage VFD2. Since the first drive transistor DX1 and the second drive transistor DX2 function as winner-take-all circuits, a high voltage of the first pixel signal and the second pixel signal is applied to the column line CL.

FIG. 6 is a timing diagram of an image sensor operation when a pixel signal is not clamped according to an exemplary embodiment of the inventive concept.

Referring to FIG. 6, the diagram shows voltages applied to different nodes during a time H-END of reading pixels in row units according to time, where the horizontal axis indicates time and the vertical axis indicates voltages. Hereinafter, a description will be provided according to time from the left side to the right side.

According to an exemplary embodiment of the inventive concept, the first pixel and the second pixel may be in a reset state. The row driver 120 may apply the selection signal SEL and the reset signal RS to the first pixel and the second pixel. For example, the selection signal SEL and the reset signal RS may be applied in an inverted state.

Referring to FIG. 6, at t61, the row driver 120 may apply a deactivated selection signal as the selection signal SEL and apply an activated reset signal as the reset signal RS so as to reset the first pixel and the second pixel. Thereafter, at t62, an activated selection signal may be applied as the selection signal SEL and a deactivated reset signal may be applied as the reset signal RS. Meanwhile, the deactivated selection signal SEL may always be applied to a remaining pixel except for the first pixel and the second pixel during the read operation of the second pixel.

In addition, at t61, the clamp controller 121 may make a first switch CLP_S1 short-circuit and make a second switch CLP_S2 be opened so as to apply the first voltage V1 to the clamp line of the first pixel. Likewise, in a case where a MUX is implemented as shown in FIG. 3B, the first voltage V1 may be selected and output. Accordingly, at t61, the clamp signal CLP1 of the first pixel has the first voltage V1, and a voltage based on a size of the first voltage V1, according to a charge distribution of a first clamp capacitor and a first floating diffusion node capacitor, is applied as the first floating diffusion node voltage VFD1. For example, in a case where the first voltage V1 is the power supply voltage VDD, the first floating diffusion node voltage VFD1 rises equally with the second floating diffusion node voltage VFD2. Both the first floating diffusion node voltage VFD1 and the second floating diffusion node voltage VFD2 may be reset to the power supply voltage VDD.

According to an exemplary embodiment of the inventive concept, at t63, the clamp controller 121 may apply the first voltage V1 to the first pixel and then the second voltage V2, which is lower than the first voltage V1.The timing generator 170 may transmit an activated selection signal SEL and a deactivated reset signal RST, and after a fixed time, the timing generator 170 may control the row driver 120 and/or the clamp controller 121 so as to apply the second voltage V2 to the first pixel by the clamp controller 121. The clamp controller 121 that has applied the first voltage V1, may make the first switch CLP1_S1 be opened and the second switch CLP1_S2 short-circuit so as to apply the second voltage V2 to the first pixel.

The voltage of the first clamp signal CLP1 and the first floating diffusion node voltage VFD1 applied to a first clamp line may decrease according to a decrease in a size of a voltage output from the clamp controller 121 at t63. In this case, since the second floating diffusion node voltage VFD2 is greater than the first floating diffusion node voltage VFD1, the pixel signal PXS is not changed. For example, a voltage level of the clamp signal CLP1 decreases by a difference between the first voltage V1 and the second voltage V2. In addition, the first floating diffusion node voltage VFD1 is reduced by a level similar to the difference between the first voltage V1 and the second voltage V2.

According to an exemplary embodiment of the inventive concept, after a reset is completed at t64, the row driver 120 may apply an activated transfer signal as a transfer signal TG2 of a second transfer transistor. As the second transfer transistor is turned on, a voltage 21 of the second floating diffusion node voltage VFD2 may be reduced by using photoelectrons generated by the second photodiode of the second pixel.

A voltage 22 obtained by subtracting the gate-source voltage of the second drive transistor from the voltage 21 which is the second floating diffusion node voltage VFD2 may be applied to the column line as the pixel signal PXS. Meanwhile, a voltage 24 obtained by subtracting the gate-source voltage of the first drive transistor from a voltage 23 which is the first floating diffusion node voltage VFD1 of the first pixel may be referred to as a clamp voltage VCLP. In this case, the voltage 21 of the second floating diffusion node voltage VFD2 is greater than the voltage 23 of the first floating diffusion node voltage VFD1. Therefore, the pixel signal PXS may be determined based on the photocharge generated by using the second photodiode of the second pixel regardless of the first pixel.

FIG. 7 is a timing diagram of an image sensor operation when a pixel signal is clamped according to an exemplary embodiment of the inventive concept. Descriptions of the operation similar to that of FIG. 6 will be omitted for convenience of explanation.

According to an exemplary embodiment of the inventive concept, after a reset is completed at t65, the row driver 120 may apply an activated transfer signal as a transfer signal

TG2 of the second transistor. The photoelectrons generated by the second photodiode of the second pixel may, as the second transistor is turned on, reduce a voltage 25 of the second floating diffusion node voltage VFD2 much more than the voltage 23 of the first floating diffusion node voltage VFD1. For example, when the light incident on the second photodiode is excessively bright, a large number of photoelectrons may be generated and the voltage value may be lowered. In this case, a voltage 24 obtained by subtracting the gate-source voltage of the first drive transistor from the voltage 23 which is the first floating diffusion node voltage VFD1 of the first pixel may be referred to as the clamp voltage VCLP.

On the other hand, a voltage 26 obtained by subtracting the gate-source voltage of the second drive transistor from the voltage 25 which is the second floating diffusion node voltage VFD2 is not applied to the column line as the pixel signal PXS. This is because the voltage 23 of the first floating diffusion node voltage VFD1 is greater than the voltage 25 of the second floating diffusion node voltage VFD2. Therefore, the pixel signal PXS is determined as the clamp voltage VCLP output by the first pixel regardless of the second pixel.

Accordingly, when excessive light comes in during the read operation of the second pixel, since the first pixel may operate such that the voltage of the pixel signal PXS may not be decreased below a predetermined value by using the clamp voltage VCLP, various pieces of noise (e.g. horizontal band noise) generated in the pixel may be prevented.

FIG. 8 illustrates the image sensor of FIG. 1 in a reset state according to an exemplary embodiment of the inventive concept. Referring to FIG. 8, the image sensor 100 may include the first pixel 111 a, the second pixel 111 b, and the clamp controller 121.

The clamp controller 121 may be connected to the plurality of pixels in row units by using the clamp line extending in the row direction of the pixel array 110. For example, the clamp controller 121 may be connected to the first pixel 111 a by using the first clamp line and be connected to the second pixel 111 b by using the second clamp line.

According to an exemplary embodiment of the inventive concept, the timing generator 170 may control an output of the clamp controller 121 corresponding to the first pixel 111 a to be the first voltage V1 or the second voltage V2 during the read operation of the second pixel 111 b, and a switch included in the clamp controller 121 corresponding to a remaining pixel may be controlled to maintain an opened state or a state only outputting the first voltage V1.

According to an exemplary embodiment of the inventive concept, based on the control signal CTR received from the timing generator 170, the first clamp signal CLP1 may have the first voltage V1, the first reset signal RS1 and the second reset voltage RS2 may each have an activated reset signal, and the first selection signal SEL1 and the second selection signal SEL2 may each have a deactivated selection signal. The power supply voltage VDD may be applied to each of the first pixel 111 a and the second pixel 111 b. In other words, the first pixel 111 a and the second pixel 111 b may be in a reset state as described with reference to FIG. 6 and FIG. 7. In this case, the first voltage V1 may be applied to the second clamp signal CLP2.

FIG. 9 illustrates the image sensor of FIG. 1 after a reset is completed according to an exemplary embodiment of the inventive concept. Referring to FIG. 9, the image sensor 100 may include the first pixel 111 a, the second pixel 111 b, and the clamp controller 121.

According to an exemplary embodiment of the inventive concept, based on the control signal CTR received from the timing generator 170, the transfer signal TG2 of the second transfer transistor may have an activated transfer signal, the first clamp signal CLP1 may have the second voltage V2, the first reset signal RS1 and the second reset signal RS2 may be a deactivated reset signal, and the first selection signal SEL1 and the second selection signal SEL2 may be an activated selection signal. The power supply voltage VDD may be applied to each of the first pixel 111 a and the second pixel 111 b.

According to an exemplary embodiment of the inventive concept, the first floating diffusion node voltage VFD1 may be decreased as the second voltage V2, which is lower than the first voltage V1, is sequentially applied to the first clamp capacitor Cp1. On the other hand, the second photodiode PD2 may output a photocurrent IPD2 and a voltage corresponding to the photocurrent IPD2 according to photoelectrons, and reduce the second floating diffusion node voltage VFD2 below the power supply voltage VDD, which is the voltage of the reset state, as the second transfer transistor TX2 is turned on.

Meanwhile, the first drive transistor DX1 and the second drive transistor DX2 may be driven by the winner-take-all circuit described with reference to FIG. 5. When the first floating diffusion node voltage VFD1 is large, the pixel signal PXS is determined by an output of the first pixel 111 a. When the second floating diffusion node voltage VFD2 is large, the pixel signal PXS is determined by an output of the second pixel 111 b. In other words, according to an exemplary embodiment of the inventive concept, when the second photodiode PD2 emits a lot of photoelectrons and the second floating diffusion node voltage VFD2 is excessively reduced, pieces of noise that may occur in the pixel may be prevented by not reducing the pixel signal PXS below the clamp voltage VCLP, which is based on the first floating diffusion node voltage VFD1.

FIG. 10 is a flowchart of an operation of an image sensor according to an exemplary embodiment of the inventive concept.

According to an exemplary embodiment of the inventive concept, in operation S310, the image sensor 100 may reset a plurality of pixels included in the pixel array 110. For example, the plurality of pixels may receive the power supply voltage VDD supplied through the reset transistor RX, and the voltage of the floating diffusion node may be reset to be the power supply voltage VDD.

Meanwhile, in operation S320, the image sensor 100 may apply the clamp signal CLP1, which decreases a voltage level from the first voltage V1 to the second voltage V2 which is lower than the first voltage V1 during a reset operation, to a first row pixel. For example, the first row pixel may include the first pixel 110 a. In this case, the first floating diffusion node voltage VFD1 corresponding to the clamp signal CLP1 may be applied through the first clamp capacitor Cpl. For example, when the voltage level of the clamp signal CLP1 is decreased since the first clamp line is electrically connected to the first floating diffusion node, the first floating diffusion node voltage VFD1 is also decreased.

Meanwhile, in operation S330, the transfer transistor of the second row pixel to which the photocharge is applied may be turned on. For example, the second row pixel may include the second pixel 111 b. A voltage corresponding to the voltage of either the first row pixel or the second row pixel may be applied as the pixel signal PXS when the second row pixel is turned on. In an exemplary embodiment of the inventive concept, when the first floating diffusion node voltage VFD1 is greater than the second floating diffusion node voltage VFD2, the first floating diffusion node voltage VFD1 may be applied to the column line as the pixel signal PXS. In other words, the pixel signal PXS may be determined by a voltage generated inside the image sensor 100, not by a signal according to light incident from outside by the second photodiode PD2. In an exemplary embodiment of the inventive concept, when the second floating diffusion node voltage VFD2 is greater than the first floating diffusion node voltage VFD1, the second floating diffusion node voltage VFD2 may be applied to the column line as the pixel signal PXS. In other words, a signal corresponding to light incident from outside may be applied to the column line as the pixel signal PXS.

FIG. 11 is a flowchart of a particular operation method of an image sensor according to an exemplary embodiment of the inventive concept.

According to an exemplary embodiment of the inventive concept, in operation S310, the image sensor 100 may reset the plurality of pixels. In operation S311, during the reset operation, a selection transistor corresponding to the first row pixel and the second row pixel may apply a deactivated selection signal and reset the floating diffusion node to the power supply voltage VDD. In this case, the first voltage may be applied to the first row pixel.

Thereafter, in operation S312, the activated selection signal may be applied to the first row pixel and the second row pixel. In this case, the deactivated selection signal may be applied to a pixel except for the first row pixel and the second row pixel.

On the other hand, in operation S321, the clamp controller 121 may apply a second voltage V2 which is lower than the first voltage V1 to the first row pixel that has received the first voltage V1. In this case, in operation S322, since a voltage corresponding to the second voltage V2 may be applied to the first floating diffusion node, the first floating diffusion node voltage VFD1 may decrease. However, in operation S323, the second floating diffusion node voltage VFD2 is maintained at the power supply voltage VDD which is a voltage in the reset state. Thereafter, in operation S331, the row driver 120 applies a signal to turn on the second transfer transistor TX2 of the second row pixel. Accordingly, in operation S332, the pixel signal PXS of the column line corresponding to the first row pixel and the second row pixel is determined based on a high voltage of the first floating diffusion node voltage VFD1 and the second floating diffusion node voltage VFD2.

FIG. 12 is a block diagram of an image processing system according to an exemplary embodiment of the inventive concept.

Referring to FIG. 12, an image processing system 400 may include an image sensor 100, an image processor 200, a display unit 500, and a lens 320.

The image sensor 100 may include the pixel array 110, the row driver 120, the ADC 130, the ramp signal generator 160, the timing generator 170, a control register block 190, and the buffer 180. The row driver 120 may include the clamp controller 121.

The image sensor 100 may sense an object 310 captured through the lens 320 by a control of the image processor 200, and the image processor 200 may output an image, which is sensed and output by the image sensor 100, to the display unit 500. The display unit 500 may include any apparatus capable of outputting images. For example, the display unit 500 may include a computer, a mobile phone, or other image output terminals.

The image processor 200 may include a camera controller 201, an image signal processor 202, and a PC I/F 203. The camera controller 201 may control the control register block 190. For example, the camera controller 201 may control the image sensor 100, e.g., the control register block 190 by using an inter-integrated circuit (I2C). However, the inventive concept is not limited thereto, and various interfaces may be applied between the camera controller 201 and the control register block 190.

The image signal processor 202 may receive an image IDTA, which is an output signal of the buffer 180, process/handle an image such that the image looks good to humans, and output the processed/handled image to the display unit 500. Alternatively, the image signal processor 202 may receive a control signal from an external host via the PC I/F 203 and provide the processed/handled image to the external host. In FIG. 12, the image signal processor 202 is shown in the image processor 200, but is not limited thereto. For example, the image signal processor 202 may be in the image sensor 100.

On the other hand, the image sensor 100 described with reference to FIG. 1 may be applied as the image sensor 100 of FIG. 12. The control register block 190 may output a control signal to the ramp signal generator 160, the timing generator 170, and the buffer 180 and control operations thereof. The control register block 190 may operate according to the control by the camera controller 201.

The pixel array 110, the row driver 120, the ADC 130, the timing generator 170, and the buffer 180 are described in detail with reference to the above-described exemplary embodiments, and thus, repeat descriptions thereof are omitted.

FIG. 13 is a circuit diagram of a clamp controller 121 c according to an example embodiment of the inventive concept.

Referring to FIGS. 1 and 13, the row driver 120 may include a clamp controller 121 c. A pixel array 110 b may include a first pixel 111 c and a second pixel 111 d. The first pixel 111 c and the second pixel 111 d are connected to the same column line CL as each other, and may be respectively referred to as a first row pixel and a second row pixel. In an embodiment, the first pixel 111 c and the second pixel 111 d may be formed adjacent to each other. In another embodiment, at least one other pixel may be formed between the first pixel 111 c and the second pixel 111 d.

Referring to FIG. 13, the clamp controller 121 c may include a first driving module 210 a, a second driving module 210 b, a first selection voltage module 220 a, a second selection voltage module 220 b, a first clamp voltage module 230 a, and a second clamp voltage module 230 b.

The first driving module 210 a and the second driving module 210 b may respectively control the first pixel 111 c and the second pixel 111 d. For example, the first driving module 210 a may respectively output a selection control signal SEL-EN and a clamp control signal SEL_CTRL to gate terminals of a first selection control transistor 221 a and a first clamp control transistor 231 a. Accordingly, transistors included in the first and second selection voltage modules 220 a and 220 b and first and second clamp voltage modules 230 a and 230 b may be switched. A transistor (for example, 221 a) shown in a dotted line may be a turned-off transistor, and a transistor (for example, 231 a) shown in a solid line may be a turned-on transistor.

The clamp controller 121 c may receive a clamp voltage VCLP and a selection voltage VSEL. The clamp controller 121 c may select the first pixel 111 c based on the clamp voltage VCLP, and may select the second pixel 111 d based on the selection voltage VSEL. In an example embodiment, the first and second selection voltage modules 220 a and 220 b and the first and second clamp voltage modules 230 a and 230 b may receive the selection voltage VSEL and the clamp voltage VCLP from the timing generator 170 (see FIG. 1) or a voltage generator. The clamp controller 121 c may apply the clamp voltage VCLP to a gate terminal of a first selection transistor SX1, and may apply the selection voltage VSEL to a gate terminal of a second selection transistor SX2. That is, the clamp controller 121 c may select the first pixel 111 c by using the clamp voltage VCLP, and may select the second pixel 111 d by using the selection voltage VSEL. Herein, a voltage level of the selection voltage VSEL may be greater than a voltage level of the clamp voltage VCLP. For example, the selection voltage VSEL may have a voltage level of 3V or more, and the clamp voltage VCLP may have a voltage level of 1V to 2V.

The first selection transistor SX1 of the first pixel 111 c and the second selection transistor SX2 of the second pixel 111 d may output the pixel signal PXS. Herein, both of the first selection transistor SX1 and the second selection transistor SX2 may be connected to the column line CL. The pixel signal PXS may be a voltage output by the column line CL. The first selection transistor SX1 and the second selection transistor SX2 may operate as a winner-take-all circuit.

Accordingly, the pixel signal PXS may be a value based on a higher voltage among a first output voltage VOUT1 of the first pixel 111 c and a second output voltage VOUT2 of the second pixel 111 d.

The first selection voltage module 220 a may include selection control transistors 221 a to 223 a, and the second selection voltage module 220 b may also include selection control transistors 221 b to 223 b. The first clamp voltage module 230 a may include the first clamp control transistor 231 a, and the second clamp voltage module 230 b may include a second clamp control transistor 231 b.

The first clamp control transistor 231 a may receive the clamp voltage VCLP from a source/drain terminal. The first clamp control transistor 231 a may, in response to the receiving of clamp control signal SEL_CTRL through the gate terminal of the first clamp control transistor 231 a, output the clamp voltage VCLP to a first gate terminal of the first selection transistor SX1. In this case, the first selection control transistor 221 a may be turned off in response to the receiving of the selection control signal SEL-EN through the gate terminal of the first selection control transistor 221 a.

The second clamp control transistor 231 b may be turned off in response to the receiving of the clamp control signal SEL_CTRL through a gate terminal of the second clamp control transistor 231 b. In this case, a second selection control transistor 221 b may receive the selection voltage VSEL from a source/drain terminal. The second selection control transistor 221 b may, in response to the receiving of the selection control signal SEL-EN through a gate terminal of the second selection control transistor 221 b, output the selection voltage VSEL to a second gate terminal of the second selection transistor SX2.

FIG. 14 is a circuit diagram of an operation of a pixel array according to an example embodiment of the inventive concept.

Referring to FIGS. 13 and 14, the first pixel 111 c is a pixel located in a first row, and the first output voltage VOUT1 of the first pixel 111 c may be a voltage for clamping the pixel signal

PXS. In addition, the second pixel 111 d is a pixel located in a second row, and the second output voltage VOUT2 of the second pixel 111 d may be a voltage based on a photo-voltage Vsig.

A voltage to be applied to the column line CL connected to the first pixel 111 c and the second pixel 111 d may be a voltage based on at least one of the first pixel 111 c and the second pixel 111 d. For example, the pixel signal PXS to be applied to the column line CL may be a higher voltage among the first output voltage VOUT1 and the second output voltage VOUT2.

According to an example embodiment of the inventive concept, during a read operation of the second pixel 111 d, the clamp controller 121 c may activate a first selection signal SEL1 based on the clamp voltage VCLP and activate a second selection signal SEL2 based on the selection voltage VSEL.

During the read operation of the second pixel 111 d, the pixel signal PXS may be have a level equal to or greater than the first output voltage VOUT1. In particular, the first output voltage VOUT1 may include a voltage level obtained by subtracting a gate-source voltage VSXgs of the first selection transistor SX1 from the clamp voltage VCLP, and the pixel signal PXS may include a voltage of the column line CL. In other words, the first output voltage VOUT1 is based on a voltage level of the clamp voltage VCLP and a voltage drop level of the first selection transistor SX1.

The second pixel 111 d may include a second driving transistor DX2. The second output voltage VOUT2 may be based on a pixel voltage VPIX, a gate-source voltage VSFgs of the second driving transistor DX2, and the photo-voltage Vsig of a second photodiode PD2. In detail, the pixel voltage VPIX may include a driving voltage driving the first pixel 111 c and the second pixel 111 d. When the second selection transistor SX2 is turned on by the selection voltage VSEL, a voltage of a second node N2 may be formed to be equal to the second output voltage VOUT2. The voltage of the second node N2 may have a level obtained by subtracting the photo-voltage Vsig and the gate-source voltage VSFgs from the pixel voltage VPIX.

FIG. 15 is a graph explaining a relationship between the clamp voltage VCLP and an analog gain according to an example embodiment of the inventive concept.

Referring to FIG. 15A, the clamp voltage VCLP may have a plurality of voltage levels, and the plurality of voltage levels may be determined by a plurality of analog gain values. In particular, a level of the clamp voltage VCLP may be changed according to an analog gain in a range in which the ADC 130 may operate normally. For example, the timing generator 170 or the voltage generator included in the image sensor 100 may receive information related to the analog gain and generate the clamp voltage VCLP corresponding to N (for example, N is one of a value from 1 to 16) times of the analog gain. When the analog gain increases, a level of the clamp voltage VCLP may have a higher voltage level.

The analog gain may be a value for amplifying an analog signal before the ADC 130 converts the analog signal to a digital signal.

Referring to FIG. 15B, the clamp voltage VCLP may limit a level of the pixel signal PXS. In this case, the clamp voltage VCLP may have a level N times the analog gain. That is, when the analog gain increases, the clamp voltage VCLP may limit a voltage level of the pixel signal PXS to a higher voltage level. Accordingly, the pixel signal PXS may be output at a level of a range ADC_SAT in which the aDC 130 may operate normally.

FIG. 16 is a flowchart of an operation of the image sensor 100 according to an example embodiment of the inventive concept.

Referring to FIG. 16, the image sensor 100 may perform a reset operation of resetting the first pixel 111 c and the second pixel 111 d in operation S410. For example, the image sensor 100 may turn on a first reset transistor RX1 of the first pixel 111 c and a second reset transistor

RX2 of the second pixel 111 d, and may charge a first floating diffusion node FD1 and a second floating diffusion node FD2 with the pixel voltage VPIX.

In operation S420, during the reset operation, the image sensor 100 may turn off the first selection transistor SX1 and turn on the second selection transistor SX2 based on the selection voltage VSEL. Descriptions thereof will be described in detail in FIGS. 17 and 18.

FIG. 17 is a timing diagram of an image sensor operation when a pixel signal is not clamped according to an embodiment of the inventive concept, and FIG. 18 is a timing diagram of an image sensor operation when a pixel signal is clamed according to an embodiment of the inventive concept. Referring to FIGS. 17 to 18, during a reset operation Reset ADC, the first selection signal SEL1 to be applied to the gate terminal of the first selection transistor SX1 may refer to a logic low, and the second selection signal SEL2 to be applied to the gate terminal of the second selection transistor SX2 may have a voltage level of the selection voltage VSEL.

Referring back to FIG. 16, in operation S430, the image sensor 100 may perform a read operation based on an output of a photodiode of the second pixel 111 d (for example, the photo-voltage Vsig).

In particular, during the read operation, the first selection transistor SX1 that has been turned off may be turned on based on the clamp voltage VCLP. In addition, in operation S440, the second selection transistor SX2 may maintain a turn-on state based on the selection voltage VSEL.

Referring to FIGS. 17 and 18, during a read operation Signal ADC, the first selection signal SEL1 may be transited to a level of the clamp voltage VCLP. In detail, at time tS, the first selection signal SEL1 may be transited from a logic low level to the level of the clamp voltage VCLP. The second selection signal SEL2 may be maintained at a level of the selection voltage VSEL.

Referring back to FIG. 16, in operation S450, the image sensor 100 may output a voltage of a higher level among the first output voltage VOUT1 of the first pixel 111 c and the second output voltage VOUT2 of the second pixel 111 d as the pixel signal PXS. The first pixel 111 c and the second pixel 111 d may be electrically connected to the same column line CL.

Referring to FIGS. 17 and 18, the first output voltage VOUT1 may be a level obtained by subtracting the photo-voltage Vsig and the gate-source voltage VSFgs of the second driving transistor DX2 from the pixel voltage VPIX. That is, as shown in FIG. 17, the first output voltage VOUT1 may be expressed by an equation of VPIX−Vsig−VSFgs. In addition, the second output voltage VOUT2 may be a clamping level. In example embodiment, the second output voltage VOUT2 may be a voltage level obtained by subtracting the source-gate voltage VSXgs of the first selection transistor SX1 from the clamp voltage level VCLP. That is, as shown in FIG. 17, the second output voltage VOUT2 may be represented by an equation of VCLP−VSXgs.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the inventive concept as set forth by the following claims. 

What is claimed is:
 1. An image sensor comprising: a pixel array comprising a first pixel and a second pixel which are electrically connected to a first column line; a row driver configured to receive a clamp voltage and a selection voltage, select the first pixel based on the clamp voltage and select the second pixel based on the selection voltage, and wherein a voltage of the first column line is determined based on a higher voltage among a first output voltage of the first pixel and a second output voltage of the second pixel during a read operation of the second pixel.
 2. The image sensor of claim 1, wherein the first pixel further comprises a first selection transistor connected to the first column line, the second pixel further comprises a second selection transistor connected to the first column line; and the row driver is configured to apply the clamp voltage to a first gate terminal of the first selection transistor, and apply the selection voltage to a second gate terminal of the second selection transistor.
 3. The image sensor of claim 2, wherein a voltage level of the selection voltage is greater than a voltage level of the clamp voltage.
 4. The image sensor of claim 2, wherein the row driver further comprises: a first clamp control transistor configured to output the clamp voltage received from a source/drain terminal to the first gate terminal in response to receiving a clamp control signal via a gate terminal of the first clamp transistor; and a first selection control transistor configured to turn off in response to receiving a selection control signal via a gate terminal of the first selection control transistor.
 5. The image sensor of claim 2, wherein the row driver further comprises: a second clamp transistor configured to turn off in response to receiving a clamp control signal via a gate terminal of the second clamp transistor; and a second selection control transistor configured to output the selection voltage received from a source/drain terminal to the second gate terminal in response to receiving a selection control signal via a gate terminal of the second selection control transistor.
 6. The image sensor of claim 1, wherein row driver further comprises: a first selection control transistor; a first clamp control transistor; and driving module configured to connected to a gate terminals of the first selection control transistor and the first clamp control transistor, output a selection control signal and a clamp control signal respectively to the gate terminals.
 7. The image sensor of claim 1, wherein the first pixel and the second pixel are pixels disposed in adjacent rows.
 8. The image sensor of claim 1, wherein the row driver activates a first selection signal of the first pixel based on the clamp voltage and a second selection signal of the second pixel based on the selection voltage during the read operation of the second pixel.
 9. The image sensor of claim 1, wherein the voltage of the first column line is greater than or equal to a value obtained by subtracting a gate-source voltage of the first selection transistor from the clamp voltage during a read operation of the second pixel.
 10. The image sensor of claim 1, wherein the first pixel is at least one pixel disposed in a first row that clamps a pixel signal, and the second pixel is at least one pixel disposed in a second row that generates an output according to a photovoltage.
 11. A pixel array comprising: a first row pixel comprising a first selection transistor receiving a clamp voltage and the first row pixel configured to generate a first output voltage in response to receiving the clamp voltage; and a second row pixel comprising a second selection transistor receiving a selection voltage configured to generate a second output voltage based on an output of a photodiode and the selection voltage, wherein a voltage applied to a column line connected to the first row pixel and the second row pixel is a voltage based on at least one of the first pixel signal and the second pixel signal.
 12. The pixel array of claim 11, wherein the voltage applied to the column line is a high voltage among the first output voltage and the second output voltage.
 13. The pixel array of claim 12, wherein the clamp voltage has a level of the plurality voltage levels, which are determined by a plurality of analog gain values.
 14. The pixel array of claim 13, wherein the clamp voltage has a higher level as the analog gain is higher, the first pixel configured to restrict the a voltage level of the voltage applied to a column line, to a higher level as the analog gain is higher.
 15. The pixel array of claim 11, wherein the first output voltage is based on a voltage level of the clamp voltage and a voltage drop level of the first selection transistor.
 16. The pixel array of claim 11, wherein the first selection transistor and the second selection transistor configured to operate as a winner-take-all circuit.
 17. The pixel array of claim 11, wherein the second row pixel further comprising a driving transistor, a value of the second output voltage is based on a pixel voltage of the second row pixel, a gate-source voltage of the driving transistor and the output of the photodiode.
 18. An operation method of an image sensor comprising a first pixel and a second pixel, the operation method comprising: performing a reset operation to reset the first pixel and the second pixel; during a reset operation, turning off a first selection transistor of the first pixel and turning on a second selection transistor of the second pixel based on a selection voltage; performing a read operation based on an output of a photodiode of the second pixel; during the read operation, turning on the first selection transistor which is turned off based on clamp voltage, and maintaining the second selection transistor in a turn on state based on the selection voltage; and outputting a higher level voltage as a pixel signal among a first output voltage of the first pixel and a second output voltage of the second pixel to a column line to which the first pixel and the second pixel are electrically connected.
 19. The operation method of claim 18, further comprising: wherein the first output voltage is based on a pixel voltage, a photovoltage and a gate-source voltage of a driving transistor included in the second pixel, and the second output voltage is based on the clamp voltage and a gate-source voltage of the first selection transistor.
 20. The operation method of claim 18, wherein the clamp voltage is applied to a gate terminal of the first selection transistor, and the selection voltage is applied to a gate terminal of the second selection transistor. 